(1) Field of the Invention
This invention relates to the fabrication of integrated circuit devices and more particularly to a method of reducing thermal stress by controlled void formation within gate spacers and trench oxide of an integrated circuit device.
(2) Description of the Prior Art
Local oxidation of silicon is the conventional lateral isolation scheme. The conventional local oxidation process (LOCOS) is described in VLSI Technology, International Edition, by S. M. Sze, McGraw-Hill Book Company, NY, N.Y., c. 1988 by McGraw-Hill Book Co., pp. 473-474. A layer of silicon nitride is deposited over a pad oxide overlying a silicon substrate. The pad oxide is a thin thermal oxide which allows better adhesion between the nitride and silicon and acts as a stress relaxation layer during field oxide formation. The nitride and oxide layers are etched to leave openings exposing portions of the silicon substrate where the local oxidation will take place. A boron channel-stop layer is ion implanted into the isolation regions. The field oxide is grown within the openings and the nitride and pad oxide layers are removed. This completes the local oxidation. FIG. 1 illustrates a conventional VLSI circuit with local oxidation before metallization. Field oxide regions 2 have been formed in and on the semiconductor substrate 1. Polysilicon gate electrodes 5 have been formed overlying a gate oxide layer 4 or field oxide regions 2. Spacers 6 have been formed on the sidewalls of the gate electrodes and all is covered with an insulating layer 7.
On pp. 476-477 of the aforementioned textbook, Sze describes some of the disadvantages of the growth of field oxide using the local oxidation method. The field oxide will penetrate under the masking nitride layer causing the space between transistors to grow during oxidation. This oxide growth under nitride is called "bird's beak encroachment." Other problems include stress in the oxide in the region covered by the nitride mask, white ribbon effect (a narrow region of nonoxidized silicon), thinning of the field oxide in narrow openings, and a non-recessed surface.
Many new isolation processes have been developed to overcome these drawbacks. Trench isolation schemes are the most attractive candidates. Typically, deep narrow trenches are used to isolate one device from another. Shallow trenches are used to isolate elements within a device, and wide trenches are used in areas where interconnection patterns will be deposited. FIG. 2 illustrates the same VLSI circuit as in FIG. 1 except that trench isolation regions 3 have been used instead of field oxide regions 2 in FIG. 1. Trench isolation can solve most of the drawbacks of the LOCOS isolation process except for stress. In addition, lightly doped drain (LDD) structures in very large scale integrated circuits (VLSI) require the formation of gate spacers which cause extreme stress in the underlying silicon substrate forming destructive defects.
Conventional integrated circuit processes are designed to be void free in the layered structure before and after metal deposition to avoid the electro/stress migration of metal. For example, U.S. Pat. No. 5,099,304 to Takemura et al discloses the formation of voids in Prior Art (FIG. 2a) as being undesirable.
However, the stress inherently comes from the thermal coefficient difference of expansion between the layers. The stress in a layer can be represented by the following: EQU S.sub.t =(a.sub.f -a.sub.s)(T.sub.r -T.sub.o) E
where S.sub.t is the stress of the current layer measured at room temperature,
a.sub.f and a.sub.s are thermal coefficients of expansion for this layer and the substrate, respectively (substrate here is defined to be the combination of all layers, including the silicon wafer, under this layer)
T.sub.r is the temperature of the layer to be thermally treated, or the formation temperature,
T.sub.o is room temperature, i.e. stress measuring temperature, and
E is Young's modulus of film.
Therefore, all thermal cycles result in thermal stress in each layer as well as in all underlying layers. The stress can be up to 5.times.10.sup.9 dynes/cm.sup.2 and even larger. The relaxation of stress results in metal failure, dielectric cracking, and defects in the silicon substrate.
U.S. Pat. No. 5,119,164 to Sliwa, Jr. et al describes a method of forming voids within a spin-on-glass layer to relieve stresses leading to cracking of the spin-on-glass layer. However, spin-on-glass cannot adequately fill some of the small spaces existing in the submicron regime. In addition, there are other drawbacks associated with using spin-on-glass as the intermetal dielectric, such as moisture outgassing, via leakage, and field inversion. It is desirable to use a material other than spin-on-glass for the trench isolation material and gate electrode spacer formation in the fabrication of integrated circuits.